PIC16F1825-E/ML【PDF 12/208 页】MCU PIC 14K FLASH 1K RAM 16QFN

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133

ATmega8515(L)

2512K–AVR–01/10

SPI Status Register – SPSR

Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if

SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low

when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by

hardware when executing the corresponding interrupt handling vector. Alternatively, the

SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing

the SPI Data Register (SPDR).

Bit 6 – WCOL: Write COLlision Flag

The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer.

The WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register

with WCOL set, and then accessing the SPI Data Register.

Bit 5..1 – Res: Reserved Bits

These bits are reserved bits in the ATmega8515 and will always read as zero.

Bit 0 – SPI2X: Double SPI Speed Bit

When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when

the SPI is in Master mode (see Table 58). This means that the minimum SCK period will

be two CPU clock periods. When the SPI is configured as Slave, the SPI is only guaran-

teed to work at f

osc/4 or lower.

The SPI interface on the ATmega8515 is also used for Program memory and EEPROM

downloading or uploading. See page 193 for Serial Programming and verification.

SPI Data Register – SPDR

The SPI Data Register is a read/write register used for data transfer between the Regis-

ter File and the SPI Shift Register. Writing to the register initiates data transmission.

Reading the register causes the Shift Register Receive buffer to be read.

Bit

7654

321

SPIF

WCOL

–

SPI2X

SPSR

Read/Write

RRRR

R/W

Initial Value

0000

000

Bit

7654

321

MSB

LSB

SPDR

Read/Write

R/W

Initial Value

Undefined

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